Telecommunications systems, cable television systems and data communication networks use optical networks to rapidly convey large amounts of information between remote points. In an optical network, information is conveyed in the form of optical signals through optical fibers. Optical fibers comprise thin strands of glass capable of communicating the signals over long distances with very low loss. Optical networks often employ wavelength division multiplexing (WDM) or dense wavelength division multiplexing (DWDM) to increase transmission capacity. In WDM and DWDM networks, a number of optical channels are carried in each fiber at disparate wavelengths, thereby increasing network capacity.
An optical signal comprised of disparate wavelengths experiences optical dispersion, an often undesirable phenomenon that causes the separation of an optical wave into spectral components with different frequencies. Optical dispersion occurs because the differing wavelengths propagate at differing speeds. The separation of an optical wave into its respective channels due to optical dispersion may require optical dispersion compensation for the particular optical signal.
In accordance with prevalent communications standards and/or protocols, nodes may communicate information in the form of Ethernet datagrams known as blocks. The size of blocks may depend on the bit rate of communication used to communicate such blocks. For example, in 10/40/100G BASE-R Physical Coding Sublayer (BR-PCS) communication, such blocks may be 66 bits in length. As another example, in 40 Gb/s Ethernet over Optical Transport Unit (OTU) communication, such blocks may be 1027 bits in length. However, prevalent optical communications standards and/or protocols are often configured such that a datagram of a different size is used to transmit data over a fiber 28 or other transmission medium. For example, in 10 Gb/s (“10G”) communication, data may be transmitted in datagrams (e.g., packets or frames) 64 bits in length. As another example, in 40 Gb/s Ethernet over OTU communication (“40G”), such datagrams may be 1024 bits in length. As a further example, in 100 Gb/s (“100G”) communication, such datagrams may be 40 bits in length. Accordingly, a 10G transmitter may reassemble a series of 66-bit blocks into 64-bit datagrams for communication wherein each 64-bit datagram may include portions of one or more 66-bit blocks. A corresponding 10G receiver may receive the series of 64-bit datagrams and reassemble such datagrams into 66-bit Ethernet blocks. Similarly, a 40G transmitter may reassemble a series of 1027-bit blocks into 1024-bit datagrams for communication wherein each 1024-bit datagram may include portions of one or more 1027-bit blocks and a corresponding 40G receiver may receive the series of 1024-bit datagrams and reassemble such datagrams into 1027-bit Ethernet blocks. Also a 100G transmitter may reassemble a series of 66-bit blocks into 40-bit datagrams for communication wherein each 40-bit datagram may include portions of one or more 66-bit blocks and a corresponding 100G receiver may receive the series of 40-bit datagrams and reassemble such datagrams into 66-bit Ethernet blocks.
The process of reassembling Ethernet blocks by a receiver may be known as “block alignment.” Block alignment may be performed by searching for a portion of an Ethernet block known as a synchronization header or “sync header.” For example, a 66-bit BR PCS Ethernet block may include a two-bit sync header. As another example, a 1027-bit Ethernet over OTU block may include a three-bit sync header.
Because a sync header will generally appear in the same bit position of each Ethernet block, the boundaries of a block may be determined by the location of a sync header within a data stream. Accordingly, by finding a sync header in a data stream, a receiver may reassemble Ethernet blocks from a data stream.
Using traditional approaches, implementation of block alignment is challenging in terms of logic size and speed. In traditional approaches, a barrel shifter is used to shift the sync bits within a block in a single clock cycle. In the 10G case, such a barrel shifter requires 66 copies of 66-bit shift registers, which is logic consuming. Alternatively, 66 copies of 66:1 multiplexers are needed to build, which is equally logic consuming. In 40G case, the problem is even more pronounced, as a 1027-bit barrel shifter would be required.